EE4143/5143 Lab Assignments


Revised by: Janusz Starzyk

Last modified: March 24, 2016

This is based on the Active-HDL Student Edition and Xilinx Vivado WebPACK

Tools Required: -

Software: -

This lab is based on Active-HDL and Xilinx Vivado. For the purpose of the lab students can use Student Edition of Active-HDL and WebPACK Edition of Xilinx Vivado.

Download Links: You will need to create free accounts to download the tools.

Active-HDL Student Edition:  http://www.aldec.com/en/products/fpga_simulation/active_hdl_student

Xilinx Vivado WebPACK: http://www.xilinx.com/support/download.html               

 Note: -

1.      On the download page select the “Vivado HLx Web Install Client” or “Vivado Design Suite - HLx Editions - Single File Download - 2015.4 Full Product Installation”. Download Vivado Design Suite and during installation select WebPACK.

 

2.      If you selected “Vivado HLx Web Install Client”, it is a web installer, i.e. a small installation file is downloaded, which in turn downloads all the required packages during installation.

 

If you selected “Vivado Design Suite - HLx Editions - Single File Download - 2015.4 Full Product Installation”, a large file (about 9 GB) will be downloaded and will probably take 30 – 60 minutes based on your internet connection.

For the download you will be redirected to a login screen, if you have Xilinx account login in using your account else create an account and fill out the details. After registration, your download should start automatically.

 

1.      NOTE: You need an active Internet connection throughout the installation process

a.       Linux: Full Installer for Linux; and

b.      Windows: Full Installer for Windows.

2.      The installer files are very large (about 10 GB) hence downloading them will take time (sometimes more than an hour).

3.      Installation requires about 10 GB of disk space and takes time (again, sometimes more than an hour).

Installation Instructions: -

Active-HDL

Xilinx Vivado WebPACK

Hardware: -

For the purpose of the lab and final project any FPGA board based on Artix-7 or higher FPGA from Xilinx can be used. FPGA development boards are available from a variety of manufacturers and their prices vary based on the FPGA used and the peripheral devices available on the board. The recommended board for this class is “Basys3 Artix-7 FPGA Board” from Digilent Inc.

Webpage: - http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/

For most students the above mentioned board is satisfactory, if you plan to use the board for later projects, you might want to look at other Xilinx development boards available.

If buying from Digilent Inc, or an authorized partner of Xilinx you might be eligible for academic discount.

Teaching Assistant (TA) Contact:

 

            Akshay Bharadwaj

Email: ab101814@ohio.edu

 

Basawaraj

Email: basawaraj.basawaraj.1@ohio.edu

NOTE: - Use “EE4143/5143” as subject

Tel: (740) 593-4553

 

Lab Hours:

                             

            Please submit your lab report to TA according to the schedule (Use the Template given in the link below). 

            Some labs have a requirement section, consisting of questions to be answered, at the end. Those questions have to be answered and the responses mailed (as pdf files) to the TA, even for labs with no report required.

 

Instructions Regarding Lab Reports and Final Project:

1.      All reports are due by end of week specified. That is, 5:00 PM EST on Friday. For example, simulation results (and requirements if any) for Lab 1 have to be submitted by 5:00 PM EST on Friday of Week 2.

2.      Mail all documents, Lab Reports, Project proposal etc., as pdf files only. Please check that all fonts and symbols appear correctly on the pdf file. All submissions are through the blackboard web site for this course.

3.      Final Project proposal due by Week 5.

4.      Final project report and code (all files needed to successfully test your design) is due by Week 14.

  1. Lab1: Getting Started with Active-VHDL          Simulation results, screen shots or printout, due Week 2. No report needed.
  2. Lab2: Getting Started with XILINX Vivado          Report due Week 3.  
  3. Tutorial 1: Structural Design using Components and Packages.
  4. Lab3: Designing BCD Up/Down Counters        Report due Week 4.    
  5. Lab4: Creating a 4-bit Adder using CORE Generator    Report Due Week 5
  6. Lab5: Top-Down VHDL Design for Xilinx FPGAs    Report due Week 8.
  7. Lab6: Final Project  Report and code: Due Week 14.

Tips for Final Project: -

1.      Decide on the topic / idea at the earliest.

2.      Testing your algorithm using Matlab®, C or any other tools / methods is helpful.

3.      Start working on the code at the earliest.

4.      Implement the code in blocks / bits. And test each one of them individually. This makes debugging easy and saves time later.

5.      Simulation of the code is an easy way to debug. First simulate then implement on the board!

6.      Remember a code that was successfully tested during simulation might still require some tweaking before it works on the board!

7.      The project is a way for you to show what you have learned in the class and how it can be used in solving various problems. It is not about how complicated and big the project is.

   

    Lab report template

 

Project Proposal Format

 

List of Projects (This list is only a suggestion. You can suggest your own projects.)

 

 

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