Designing a VHDL model for
the MC14510B and a Cascaded 8-bit Counter
Revised by: Basawaraj
Last modified: 02/11/2014
Introduction
In lab 1, you were actually given the VHDL model for the chip 74161 counter to compile and simulate. One task of a VHDL Design Engineer in industry is to write hardware descriptions of IC's that are already in existence. Many clients, especially the military, now require IC manufacturers to document the hardware descriptions of their Integrated Circuits in VHDL or Verilog (another hardware description language). In this lab, your task is to describe and simulate a bi-directional counter in VHDL. The counter you will model is a MC14510B. This counter is similar to the 74161, so you can use it as a starting point for your design. After finishing the design of MC14510B, you should implement an 8-bit BCD up/down Counter.
Background
for Starting
Read through the datasheet of MC14510B. Make sure you understand the specification of the device, including the pin description, the truth table and the timing diagram, before you start coding. Complete Data Sheet is available (PDF 281k): Download. The main function of this device is described here.
· MC14510B is a BCD counter.
· MC14510B can count up or down.
· The output of the counter can be preset to an arbitrary value by bringing Preset_Enable high.
· Clear (Reset) operation is performed asynchronously and is active-high.
· In the MC14510B, when counting up, the Carry Out signal is normally high, and is low only when Q1 and Q4 are high and Carry In is low. When counting down, Carry Out is low only when Q1 through Q4 and Carry In are low.
· If input number bigger than 9 (an illegal state) is loaded, the MC14510B will processes differently depending upon the UP/DOWN signal. Check the data sheet carefully, especially the UP counting mode in which the temporary states should be handled separately. Be sure to include all the possible state process in your program.
Requirements
· The project should be finished by using Active-HDL.
· Create your project working directory under E:\VHDL\Lab3.
· The project includes two parts:
1. Implement MC14510B by using VHDL behavioral
architecture. Design an entity called
"MC14510B" and specify the input and output port names given
in the Block Diagram of the data sheet. It is important that you use the same
port names, since I will be testing your design with my own stimulus file for
proper functionality.
2. Implement a Presettable Cascaded 8-bit BCD
Up/Down Counter, ranging from 0~99 by using two MC14510B you designed in
the first step. Refer to the data sheet of MC14510B to get more details. You
can use structural description. (Hint: Use
PACKAGE to include your component MC14510B
and include the library that has the component MC14510B.)
· Compile and simulate your design (Note: use Run Until or Run For. Don't use Run. Sometime you cannot stop the running when executing Run command.) .
· Make sure you test all functions of the counter described above. Coming up with a good test sequence is just as important as writing the code! Use the timing diagram in the data sheet as a guide. Include conditions not given in the timing diagram (such as illegal states) to receive full credit.
· After you have completely tested your design, print a copy of the waveform and pencil-in the different tests you performed.
·
Write a detailed report (Max. of 6 Pages).
Turn in your report in lab, and email your VHDL files to TA by the next lab time.
Extra Credit
Extra credit will be given to the designs that are implemented efficiently using the shortest code to get the job done. Extra credit will also be given to the simulations that are organized so that all functions of the chip are tested with the minimum number of steps.
Note: - Make use of Comments wherever you feel they are required.