Lab 4: Creating a 4-bit Adder Using the Xilinx IP CORE Generator

Xilinx Vivado Version: 2015.4 WebPACK

Last modified: 03-29-2016

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Introduction

In this lab, you will create a 4-bit adder with carry input and output along with a clock enable by using the Xilinx CORE Generator and instantiate the Adder in a top-level VHDL file. This lab helps familiarize you with the Xilinx IP CORE Generator and the Xilinx implementation tools by having you generate the Adder as an IP core. This lab is completed using the Xilinx Vivado 2015.4 WebPACK software. You use a typical VHDL flow to black-box (instantiate) the core into a top-level piece of VHDL code, synthesize your design, and take the synthesized design through the Xilinx implementation tools.

Objectives

After completing this lab, you will be able to:

· Generate a CORE Generator macro

· Synthesize the VHDL and black-box instantiations through synthesis

· Implement a synthesized design through the Xilinx implementation tools

Design Description

Use the CORE Generator to create a 4-bit adder that has the following characteristics:

· Two input data width of 4-bits of unsigned data

· Carry in and out.

· Clock enable

· Asynchronous output data width of 4 bits.

Procedure

Start the Project Navigator and Open the Project

Generate a 4-bit Adder Using the CORE Generator

Add the CORE Generator Macro intoYour VHDL Code

Note: For your reference, your code should be similar to

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_top is

Port ( a_in : in STD_LOGIC_VECTOR (3 downto 0);

b_in : in STD_LOGIC_VECTOR (3 downto 0);

clk : in STD_LOGIC;

clk_en : in STD_LOGIC;

carry_in : in STD_LOGIC;

carry_out : out STD_LOGIC;

c_out : out STD_LOGIC_VECTOR (3 downto 0));

end adder_top;

architecture Behavioral of adder_top is

COMPONENT c_addsub_0

PORT (

A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK : IN STD_LOGIC;

C_IN : IN STD_LOGIC;

CE : IN STD_LOGIC;

C_OUT : OUT STD_LOGIC;

S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COMPONENT;

begin

inst_1: c_addsub_0

port map

(

A => a_in,

B => b_in,

CLK => clk,

C_IN => carry_in,

CE => clk_en,

C_OUT => carry_out,

S => c_out

);

end Behavioral;

Synthesize the whole design.

Conclusion

You learned the basic design flow for taking a VHDL design with IP CORE Generator macros through the design process, which includes the following:

· Understanding the basics for generating a IP CORE Generator macro

· Knowing how to synthesize a design containing IP CORE Generator macros through synthesis.

Try It Out:

Implement this design on to your board.

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