EE715

Lab Reports

Each student is expected to submit a brief written summary of the results they obtained. This report should consist of three sections:

VLSI design
Each student's VSLI layout of the design must be presented in relation to the selected project - transistor level schematic and the inner working of the circuit.
Simulation:
Any results obtaind in circuit design, e.g. graphs, calculations, etc., should be carefully analysed in relation to the "ideal' text book solutions.
Discussion:
In particular, possible explanations for any discrepancies between observed and expected results.

The best reports are brief and demonstrate a student's insight and understanding of the lab/lecture material. These labs comprise the bulk of the graded material in this course. If needed, the following advise about writing up lab reports will result in higher grades for you and less frustration for your TA.

In general, a well organized lab is easier to read, and we are then better able to pick out the important points in your analysis. We expect the following things from your analysis: