VLSI implementation of a high speed delta-sigma A/D converter

Zheng Chen

Implemented an oversampling delta-sigma A/D conversion for 1M Hz signal (50M Hz sampling rate) in mixed-signal IC using 0.8 micron CMOS process (from MOSIS). Designed a third-order analog modulator including switched capacitor integrators, comparator, bias circuitry, and 3-bit flash A/D and D/A converters. Fulfilled the digital decimator (comb filter, and FIR low-pass filter bank) in VHDL. Full-custom layout for analog circuit while standard cell layout for digital.