Ohio University
School of Electrical Engineering and Computer Science
ECE 617 - Fault Testable Design
Course Schedule
Spring 2010
Wk 
Date 
Subject 
Reading 
Homework
1 
Introduction
Due dates

 Mar 30 Class organization Handout1,Ch.1,notes1, Homework is due by the date indicated.  Late HW and computer assignments will lower the assignment grade as follows:

   Digital fault and test concepts, Physical faults and system reliability Handout2,Ch.2,notes2,

1 day late -10%

up to 1 week late -25%

up to 1 month late -50%

> 1 month late -75%

Modeling
2 
 Apr 6 Functional fault modeling, Fault detection Handout3,Ch.3,notes3
 HW 1

   Fault models and path sensitization, Boolean algebra
HW 2: 1.2, 1.5, 1.6
Design and Simulation

3

 Apr 13 Controllability and Observability Handout4,Ch.4,notes4
  
    Logic simulation, Element models and evaluation Handout5,Ch.5,notes5
 HW 3: 2.1, 2.6, 

   Hazards, Event driven simulation, Deductive simulation, Ch. 5 Lab. 1 
4
 Apr 20

Test Generation and Fault modeling



 Critical path, Handout6,Ch.6,notes6  

    D-algorithm, Ch.6,notes6 HW 4: plus prove Boolean identities

Lab. 2  Lab report for Lab 1 due

5
 Apr 27 PODEM and FAN, Rajski's method Ch.6,notes6

  Current Testing,  Handout7,Ch.7,notes7
 Lab. 3  Lab report for Lab 2 due

6

 May 4

Fault simulation

    
    Fault equivalence and fault dominance,  Handout8,  5.6,notes8,  

7

 May 11 Midterm
 chs. 1-6
 Midterm 2003
Fault simulation techniques
 Handout9, 5.7 notes9
 HW 5: 6.1 and 6.3 test only two faults, Use critical path on Fig. P6.2

  8

 May 18

Functional Testing

    Random test generation Handout10,6.2.3,notes10,
  
    FSM testing, ATG in sequential circuits, Delay faults Handout11,Ch6, notes 11
  

  9

 May 25
Design for testability
 
Design for Testability, Ad hoc techniques, Iterative array test Handout12, Ch. 8, notes 12
 HW6: 5.2 , 5.3  

Lab. 4  Lab report for Lab 3 due

    Scan Path Design

Handout 13, Ch. 9,

notes 13,

HW 7: 6.5, 6.6

Lab assignment

10

 Jun 1 Built-in self test, Compression techniques

Handout 14, Ch. 11, 

notes 14, 

  Boundary scan designs

Handout 15, Ch. 10,

notes 15

HW 8: 11.1, 11.4,11.5

 Tuesday, June 8, 8:00 am Final Exam Final exam topics

Notes: Chapter sections are from the text by S. Mourad, Y. Zorian, "Principles of Testing Electronic Systems", John Wiley & Sons, 2000.