VHDL Design
EE 414/514 (Call#19139/19141 )
Fall Quarter, 2011
Class web page: http://www.ohio.edu/people/starzykj/network/Class/ee514/index.html
10:10-11:30 a.m. ACR r. ??? T,Th
Professor: Dr. Janusz Starzyk
Office hours Tuesday, Thursday 2-3; other hours by appointment.
Office location - Stocker 347.
TA Basawaraj Email: bb593707@ohio.edu Tel: (740) 593-4995 Rm. 323 Stocker
Text
K.C. Chang, "Digital Design and Modeling with VHDL and Synthesis", IEEE Computer Society Press, 1997
Reference
· P.P. Chu,
"RTL Hardware Design Using VHDL",Wiley-IEEE
Press, 2006.
· K.C. Chang,
"Digital Systems Design with VHDL and Synthesis", IEEE Computer
Society Press, 1997.
· P. Ashenden, "The Designers Guide to VHDL, P. Ashenden", Morgan Kaufman Publishers, 1995.
· Zainalabedin Navambi, "VHDL Analysis and Modeling of Digital
Systems", Mc. Graw Hill, 1993.
· VHDL web resources
http://www.cs.ucr.edu/content/esd/labs/tutorial/VHDL_Page.htm
http://cwc.ucsd.edu/courses/billlin/ece111/VHDL-material.html
Course Description
In recent years, there has been a trend toward using very high speed hardware description languages (VHDL) for circuit specification. Creating a VHDL model has similarity to writing a software program. The conciseness of VHDL models made them preferable to the corresponding flow, state, and logic diagrams. Circuits can be modeled using various abstraction levels. Powerful synthesis methods capable of generating detailed gate level or transistor level schematics using VHDL description of the designed architectures were developed and implemented in CAD tools. Xilinx Foundation software and FPGA chips, ActiveHDL and Mentor Graphics tools, permits our students to use the state of the art design environment.
Course outline
· Design of
microelectronic circuits
· Behavioral modeling of
electronic circuits
· Abstract hardware
models
· Compilation and
behavioral optimization
· Computer-aided
synthesis and optimization
· Architectural synthesis
· Scheduling algorithms
· Modeling of
component libraries
Laboratory Work
All students are expected to complete design projects assigned in the VHDL design lab. Students will use a new set of design software tools (Xilinx Synthesis Technology XST, and Aldec ActiveHDL), which facilitate the design and simulation of the architectures described by the VHDL code.
Grading
Grades will be based on the following;
· Midterm examination
(15%)
· Homework (15%)
· Laboratory Assignments
(45%)
· Final examination
(25%)
Examinations
Midterm - Oct. 25,
2011.
Final examination - Tuesday, November 22, 2011, at
8:00 a.m.
All examinations are closed books and notes.
Students may have one sheet with formulas as a help during each exam.
Students with Disabilities
If you have a documented disability that requires an accommodation, please notify me within the first two weeks of the quarter. Please contact the Office of Institutional Equity for guide and assistance with disability issues. Their web page is
http://www.ohio.edu/equity/disabilityservices/
Withdrawal
A student may withdraw from class at his discretion up to and including the first 21 days of the quarter.
Academic Conduct
Cheating on examinations, submitting work of other students as your own, or plagiarism in any form will result in penalties ranging from an F on the assignment or exam to expulsion from the university, depending on the seriousness of the offense.
Classroom Privacy
The lectures, classroom activities, and all materials associated with this class and developed by the instructor are copyrighted in the name of Dr. Janusz Starzyk. Recording of classroom activities by any electronic means, by students, other faculty, university administrators, or others, requires permission of the instructor. Under no circumstances may verbatim recording of copyrighted classroom lectures and materials by electronic or any other means (including note taking) be conducted for 1) sale, whether or not it is for educational benefit, or 2) for the educational benefit of those not enrolled in the class. This does not apply to non-verbatim notes taken by students.