Ohio University
School of Electrical Engineering and Computer Science
ECE 414/514- VHDL Design
Course Schedule, Fall 2011
Updated on Wednesday, August 17, 2011
Please check this schedule frequently as it is often updated.

Wk	Dates	Subject	Reading	Homework
1	Sep 6	Introduction
		Class and lab organization, overview of VHDL technology	1.1 - 1.5 cookbook.1 cookbook.2  & Evita 1.3 and 2 , Download Evita, Entity Architecture	Late HW and computer assignments will lower the assignment grade as follows:
		Introduction to VHDL, package, entity, architecture, names Discuss VHDL Lab organization and final projects	2.1 - 2.9,VHDL notes, slides 2	1 day late -10% up to 1 week late -25% up to 1 month late -50% > 1 month late -75%
2	Sep 13	VHDL modeling	VHDL jobs
		VHDL Lab 4:30 6:30 pm r. 305	VHDL jobs
		Concurency, process, delta time, signals	3.1-3.6, Evita 3 signals, slides 3,
		Sequential statements	VHDL jobs
		Signal and variable assignment, if, case and loop statements	4.1-4.5, slides 4a, Evita 6
3	Sep 20	Null statement, Procedure call statement, Return statement	4.6-4.12, slides 4b	Homework 1
		Concurrent Statements	chapter 4 problems
		Assert, and wait statements, process, conditional signal assignment,	5.1-5.2, slides 5, Evita 8
		Subprograms and Overloading
4	Sep 27	Component declaration and instantiation, generate, block,	5.3-5.8	Homework 2
		Subprogram, package, resolution function, Overloading,	6.1-6.6 slides 6 , Evita 7
5	Oct 4	Structural Modeling	Evita request from Aldec
		Return values and type casting, guard,	Evita 4 - Entity, port, generics 6.7-6.8
	Oct 6	No class - Discuss final projects in extra lab sessions
6	Oct 11	No class - Discuss final projects in extra lab sessions
	Oct 13	Design unit, generics,	7.1-7.3 slides 7
7	Oct 18	Configuration specification,  configuration declaration, library	7.4-7.7, Evita 5
		Writing VHDL for Synthesis	A VHDL Synthesis Navambi   =>	Homework 3
		A design case, Simulation, writing a test bench, Test bench, design synthesis	11.1-11.6  slides 11 slides 11a Evita 9	Homework 3
8	Oct 25	Midterm	chapters 1-7 midterm solution
		Behavioral Modeling	Embedded Systems Design
		Files, ROM, bidirectional pads, attribute, access and record types, guarded blocks, signals, disconnection	10.1-10.9 slides 10
9	Nov 1
		FSM output, synthesis	9.4-9.5 slides 9
	5-7 pm RTC 140	Final Project Presentation - use Power Point 8-10 min per student (show architecture, final mapping, discuss simulation and test results)	Speaker Feedback Form
		Writing VHDL for Synthesis	A VHDL Synthesis Navambi   =>	Homework 4
		General guidelines, combinatorial synthesis	8.1-8.3,  Overview RASP
10	Nov 8	Registers, latches, buffers, MUXs, operators	8.4-8.6,
	5-7 pm r. 306	Final Project demonstration in lab Designs must be mapped to the Xilinx board and tested
		Simulation vs synthesis, synthesis process	8.7-8.10,slides 8a
		Spartan chips, Synthesis	9.1-9.3slides 8b
		CPU Modeling and Design	Parwan slides
		ALU design	slides 1112.1-12.4 Xilinx University Program
	Tuesday, November 22, 2011, at 10:00 a.m.	Final Exam	past final

Notes: Chapter sections are from the text by K.C. Chang, Digital Design and Modeling with VHDL and Synthesis.

Homework is due the first class in the week  indicated.