Homework 4 (40 points)

1. Write a function that takes two parameters and returns their Greatest Common Factor (GCF). For example, GCF of 8 and 12 is 4. Simulate your VHDL code. (7 points)

2. Write a procedure that sorts an array of integers in non-decreasing order. Simulate your VHDL code. (7 points)

3. Write procedures MUX31 and MUX41 so that the code can be synthesizable with type std-logic and std-logic-vector. (5 points)

4. What is the purpose of a package body? What is the purpose (and the restrictions) of the declaration items inside a package body? (4 points)

5. Discuss whether a local variable, a signal, a constant, a type (subtype), and a subprogram can be declared in the package, package body, subprogram, process statement. (4 points)

6. The following VHDL code shows two architectures to assign signal Y. Is architecture SEQUENTIAL valid? What would be the value of signal Y? Is architecture CONCURRENT1 valid? If it is valid, what would be the value of signal Y. If it is not valid, why? Is architecture CONCURRENT2 valid? If it is valid, what would be the value of signal Y If it is not valid, why? (9 points)

1 entity SEQCON is
2 end SEQCON;
3 architecture SEQUENTIAL of SEQCON is
4 signal Y : bit;
5 begin
6 p0: process
7 begin

8 Y <= '1';
9 Y<= '0';
10 wait for 20 ns;
11 end process;
12 end SEQUENTIAL;
13 architecture CONCURRENT1 of SEQCON is
14 signal Y : bit;
15 begin
16 Y <= '1';
17 Y <= '0' ;
18 end CONCURRENT1;
19 architecture CONCURRENT2 of SEQCON is
20 signal Y : bit;
21 begin
22 Y <= '1' ;
23 Y <= '1';
24 end CONCURRENT2;

7. In the following VHDL code, which procedure declaration is valid? Explain. (4 points)

1 package CONIO is
2 procedure CON_INOUT( constant DIN : inout bit);
4 procedure CON_BUFFER( constant DIN : buffer bit);
6 procedure CON_LINKAGE( constant DIN : linkage bit);
8 procedure DEF_CON_INOUT( DIN : inout bit);
10 procedure DEF_CON_BUFFER( DIN : buffer bit);
12 procedure DEF_CON_LINKAGE( DIN : linkage bit);
14 end CONIO;