Homework 2 (30 points)
1. Write VHDL code to have input DIN and output DOUT with 8-bits each. DOUT is the 2's complement of DIN. Hint: scan through from LSB (Least Significant Bit), DOUT(1) is the same as DIN(1) until '1' is encountered. after that DOUT (i) <= not DIN(i). Simulate your VHDL code. (7 points)
2. In PCI (Peripheral Components Interconnect), even parity is used across the address data bus AD (32 bits) and command byte enable CBEN (4 bits). To check parity AD bus is appended with CBEN and the PCI checks if the number of ones in the combined word are even. If negative, then the parity check bit is set to 1. Write VHDL code to have AD and CBEN as inputs and PARITY as output. Simulate your VHDL code. (7 points)
3. Write a process statement to generate a clock signal with a period of 30 ns and 50 percent duty cycle. (3 points)
4. Can you name all the VHDL sequential statements? Where do they appear? (3 points)
5. Can a process have a sensitivity list and a wait statement inside the process statement body? Why? (3 points)
6. The following VHDL code models a JK flipflop.
Note that Q is an output port which cannot be read (evaluated). Which
architecture(s) implement(s) the correct function of a JK flipflop? Verify your answers and reasons by simulating the
code. (7 points)
1 entity JKFF is
2 port (
3 CLK, RSTN, J, K : in bit; 4 Q : out bit); 5 end JKFF;
6 -------------------------------------------------
7 architecture RTL of JKFF is 8 signal FF : bit; 9 begin
10 process (CLK, RSTN)
11 variable JK : bit_Vector (l downto 0);
12 begin
13 if (RSTN = '0') then
14 FF <= '0' ; 15 elsif (CLK' event and CLK = '1') then 16 JK := J & K; 17 case JK is
18 when "01" => FF <= '0';
19 when "10" => FF <= '1';
20 when "11" => FF <= not FF;
21 when "00" => FF <= FF;
22 end case;
23 end if;
24 end process;
25 Q <= FF;
26 end RTL;
27 ----------------------------------------------------------------------------
28 architecture RTL1 of JKFF is 29 signal FF : bit; 30 begin
31 process (CLK, RSTN)
32 begin
33 if (RSTN = '0') then
34 FF <= '0';
35 Q <= '0' ;36 elsif (CLK'event and CLK = '1') then
37 if (J = '1') and (K = '1') then
38 FF <= not FF;
39 elsif (J = '1') and (K = '0') then 40 FF <= '0' ; 41 elsif (J = '0') and (K = '1') then 42 FF <= '0';
43 end if;
44 end if;
45 Q <= FF;
46 end process;
47 end RTL1;
48 -------------------------------------------------
49 architecture RTL2 of JKFF is 50 signal FF : bit; 51 begin
52 process (CLK, RSTN)
53 begin
54 if (RSTN = '0') then
55 FF <= '0';
56 Q <= '0';
57 elsif (CLK'event and CLK = '1') then
58 if (J= '1') and (K = '1') then
59 FF <= not FF;
60 elsif (J = '1') and (K = '0') then 61 FF <= '1' ; 62 elsif (J = '0') and (K = '1') then 63 FF <= '0';
64 end if;
65 Q <= FF;
66 end if;
67 end process;
68 end RTL2;
69 -------------------------------------------------
70 architecture RTL3 of JKFF is 71 begin
72 process (CLK, RSTN)
73 variable FF : bit; 74 begin
75 if (RSTN = '0') then
76 FF := '0'; 77 Q <= '0';
78 elsif (CLK'event and CLK = '1') then
79 if (J = '1') and (K = '1') then
80 FF := not FF; 81 elsif (J = '1') and (K = '0') then 82 FF := '1'; 83 elsif (J = '0') and (K = '1') then 84 FF := '0'; 85 end if;
86 Q <= FF;
87 end if;
88 end process;
89 end RTL3;