Homework 3 (30 points)

1. "S <= A;" is a signal assignment statement. Could it be a sequential statement? Could it be a concurrent statement? How do we tell? If it is a concurrent statement. is it a conditional signal assignment statement or a selected signal assignment statement? (4 points)

2. The following VHDL code shows four examples of the concurrent procedure call. Determine whether each procedure is valid or not, and why. (8 points)

1 entity PROCALL_EX is 
2 end PROCALL_EX; 
3 architecture RTL of PROCALL_EX is 
4 procedure ANDOR ( 
5 signal A, B, C, D : in bit_vector(1 downto 0); 
6 signal Y : out bit_vector(1 downto 0)) is 
7 begin 
8 Y <= (A and B) or (C and D); 
9 end ANDOR; 
10 signal DIN, DOUT : bit_vector(7 downto 0); 
11 signal X, Y, Z : bit_vector(1 downto 0); 
12 begin 
13 call0: ANDOR (A => DIN(7) & DIN(6), B => DIN(5 downto 4), 
14 C => DIN(3 downto 2), D => DIN(1 downto 0), 
15 Y => DOUT(1 downto 0)); 
16 call1: ANDOR (A => DIN(7 downto 6), B => DIN(5 downto 4), 
17 C => DIN(3 downto 2), D => DIN(1 downto 0), 
18 Y => DOUT(3 downto 2)); 
19 call2: ANDOR (A => DIN(7 downto 6) and DIN(5 downto 4), 
20 B => DIN(5 downto 4), 
21 C => DIN(3 downto 2), D => DIN(1 downto 0), 
22 Y => DOUT(5 downto 4)); 
23 call3: ANDOR (A => X nand Y, B => Z, 
24 C => DIN(3 downto 2), D => DIN(1 downto 0), 
25 Y => DOUT(7 downto 6)); 
26 end RTL; 
 

3. Can a local variable be used as an actual parameter for a concurrent procedure call statement? (2 points)

4. Can a component be declared inside the process declaration part? Explain why? (4 points)

5. Rewrite the following VHDL code (which is a BCD to 7-segment encoder) to use concurrent signal assignment statements. (7 points)

1 entity IFCASE is 
2 port ( 
3 HEX: in bit_vector(3 downto 0); 
4 LED: out bit_vector(6 downto 0)); 
5 end IFCASE; 
6 ----------------------------------------------- 
7 architecture RTL of IFCASE is 
8 begin 
9 p0 : process (HEX) 
10 begin 
11 case HEX is 
12 when "0000" => LED <= "1111110"; 
13 when "0001" => LED <= "1100000"; 
14 when "0010" => LED <= "1011011"; 
15 when "0011" => LED <= "1110011"; 
16 when "0100" => LED <= "1100101"; 
17 when "0101" => LED <= "0110111"; 
18 when "0110" => LED <= "0111111"; 
19 when "0111" => LED <= "1100010"; 
20 when "1000" => LED <= "1111111"; 
21 when "1001" => LED <= "1110111"; 
22 when "1010" => LED <= "0111001"; 
23 when "1011" => LED <= "0111101"; 
24 when "1100" => LED <= "0011001"; 
25 when "1101" => LED <= "1111001"; 
26 when "1110" => LED <= "1011111"; 
27 when others => LED <= "0001111"; 
28 end case; 
29 end process; 
30 end RTL; 
31 ----------------------------------------------- 
32 architecture RTL1 of IFCASE is 
33 begin 
34 p0: process (HEX) 
35 begin 
36 if HEX ="0000" then LED <= "1111110"; 
37 elsif HEX ="0001" then LED <= "1100000"; 
38 elsif HEX ="0010" then LED <= "1011011"; 
39 elsif HEX ="0011" then LED <= "1110011"; 
40 elsif HEX ="0100" then LED <= "1100101"; 
41 elsif HEX ="0101" then LED <= "0110111"; 
42 elsif HEX ="0110" then LED <= "0111111"; 
43 elsif HEX ="0111" then LED <= "1100010"; 
44 elsif HEX ="1000" then LED <= "1111111"; 
45 elsif HEX ="1001" then LED <= "1110111"; 
46 elsif HEX ="1010" then LED <= "1110011"; 
47 elsif HEX ="1011" then LED <= "0111101"; 
48 elsif HEX ="1100" then LED <= "0011001"; 
49 elsif HEX ="1101" then LED <= "1111001"; 
50 elsif HEX ="1110" then LED <= "1011111"; 
51 else LED <= "0001111"; 
52 end if; 
53 end process; 
54 end RTL1; 

6. The preceding VHDL code shows two architectures for entity IFCASE. Do they describe the same function? Is one of them better than the other? Explain why. (5 points)