Design of Digital Circuits
EE 4143/5143 (Call# 9069/9077)
Spring Semester 2014
Web: www.ent.ohiou.edu/~starzyk,
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Class Schedule Class Web Page |
http://www.ohio.edu/people/starzykj/network/Class/EE5143/index.htm |
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Professor Office hours Email:
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Dr. Janusz Starzyk, M, Fr, 2-3, Stocker 347; other hours by appointment, tel 593-1580;
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TA Office
hours
email: |
Basawaraj, M. W. 3-5 Rm. 375, Stocker, tel: 593-4995; |
Text
K.C. Chang, "Digital Design and Modeling with VHDL and
Synthesis", IEEE Computer Society Press, 1997
References
J. M. Rabaey,
A. Chandrasakasan, B. Nikolic
"Digital Integrated Circuits - A Design Perspective", Prentice Hall,
2003.
P.P.
Chu, "RTL Hardware Design Using VHDL",Wiley-IEEE Press, 2006.
K.C.
Chang, "Digital Systems Design with VHDL and Synthesis", IEEE
Computer Society Press, 1997.
Course outline
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· Design
of microelectronic circuits · Behavioral
modeling of electronic circuits · Abstract
hardware models using VHDL · Sequential
process, functions, procedures and signals · Compilation
and behavioral optimization · Concurrent
statements and components · Configuration,
generics, test bench · Computer-aided
architectural synthesis · Modeling
of component libraries · Progress
and impacts of MOS technology · Design
metrics · MOS
transistor and CMOS gates · Transient
behavior · CMOS
inverter characteristics and dynamics · Combinatorial
logic dynamics · Sequential
logic |
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Project and Lab Work
All students are expected to complete design projects assigned
in the VHDL design lab. Students will use design software tools (Xilinx Synthesis
Technology XST), which facilitate the design and simulation of the
architectures described by the VHDL code. Supervised tutorials will be provided
to teach students how to use the tools.
Learning the tools is detrimental to completion of the final design
project.
Lab M. 2-4 p.m. r. 192
Grading
Grades will be based on the following;
Homework and Laboratory Assignments (15%) graded based on the
completion of all labs
Midterm (20%)
Design Project (40%) - weights within project are as follows:
Project proposal written report (20%)
Completed design simulation and testing
(20%)
Class ppt
presentation (20%)
Working circuit demo (20%)
Final written report
(20%)
Final exam (25%)
Examinations
Midterm – Wednesday, Feb 26,
2013.
Final
examination - Monday, April 28, 2013 at 10:10 a.m.
All examinations are closed books
and notes. Students may have one sheet with formulas as a help during each
exam.
Attendance
Attendance is not required but highly recommended.
Homework
All homework must be neatly done and handled in on time. Returning late homework will result in reduction of the homework grade.
Students with Disabilities
If you have a documented disability that requires an accommodation, please notify me within the first two weeks of the quarter. Please contact the Office of Institutional Equity for guide and assistance with disability issues. Their web page is
http://www.ohio.edu/equity/disabilityservices/
Withdrawal
A student may withdraw from class at his discretion up to and including the first 10 weeks of the semester.
Academic Conduct
Cheating on examinations, submitting work of other students as your own, or plagiarism in any form will result in penalties ranging from an F on the assignment or exam to expulsion from the university, depending on the seriousness of the offense.
Classroom Privacy
Recording of classroom activities by any electronic means, by students, other faculty, university administrators, or others, requires permission of the instructor. Under no circumstances may verbatim recording of copyrighted classroom lectures and materials by electronic or any other means (including note taking) be conducted for 1) sale, whether or not it is for educational benefit, or 2) for the educational benefit of those not enrolled in the class. This does not apply to non-verbatim notes taken by students.